Volt Blocking
Volt Blocking
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Achieving Flexible Power Management for Embedded Systems
Embedded designers today are facing more and more pressure to increase battery life and at the same time offer more features. One only needs to look at the rapid increase of functionality in mobile handhelds for verification. It has become clear that battery chemistries are not improving at the needed rate to fulfill these requirements. This places the pressure squarely on silicon vendors to deliver better performance at lower power. As if this dilemma wasn’t challenging enough, designers face strict time to market requirements posed by shrinking design cycles.
Moreover, green movements are requesting a reduction in battery waste, which translates to embedded systems that require fewer battery changes. There are also government regulations (Example: Energy Star) across the globe to reduce stand-by current in appliances. The next generation of embedded systems is going to need extremely low active and sleep power consumption while simultaneously increasing the amount of flexibility and programmability needed to meet time-to-market requirements.
Apart from lower current consumption, there is also a need to lower system voltage. A few years ago, the standard for minimum operating voltage was 3.3V. Today, it is 1.8V. Charting this trend, it is realistic to extend this trend into the sub-volt range for tomorrow’s devices. This opens up the ability to build Psoc-based designs with a single AA battery (whose end of life voltage is around 0.9V). Although some Psoc-based designs can run at 1.8V today, quite often the analog
performance degrades with such low voltages. For handheld battery powered designs that require good analog performance, systems that can run at below 1 volt voltage and still meet the analog performance requirements, offer the ability to move to a single AA battery. This translates to lower cost to the consumer and fewer batteries.
How to achieve sub-volt operation?
Sub-volt operation can be achieved when the embedded Psoc device has a boost converter built-in that is able to boost the input voltage (example: 0.9V input voltage) to a higher system level voltage (example: 3.3V). In this mode, it is important that the noise from the boost converter does not affect the performance of analog peripherals. Figure 1 shows the system level connections for an integrated boost converter that is a part of a Psoc 3 programmable system-on-chip from Cypress Semiconductor.
The Psoc 3 and Psoc 5 families are field-programmable embedded Psocs that have programmable digital blocks and configurable analog blocks. These devices are designed to offer flexibility and programmability to the user while consuming very low sleep and active current. The architectures also offer precise analog performance (16-bit to 20-bit precision). The families are supported by Psoc Creator software, an integrated development environment that can be used to rapidly develop designs from end to end – all the way from device selection, configuring/programming the digital and analog peripherals, configuring the Power System, firmware development, debug and programming.
Having an integrated boost converter that can accept sub-volt input voltages has the following advantages:
1. Ability to run the system from a single AA battery.
2. Ability to provide a guaranteed minimum system voltage even with a varying supply voltage
3. Ability to use the boost output voltage to run other circuitry in the system that needs higher voltage. Example: LCD glass,
Sensor circuits, etc
Wide-supply voltage range
Having a wide supply voltage range that spans from 1.8V (0.9V with boost enabled) to 5.5V provides maximum flexibility to the
user due to the following reasons:
1. Can span standard battery voltage ranges for most common batteries through their end of life voltage as shown in table 1.
2. Compatible to legacy system voltages of 3.3V and 5V.
3. Upper end of 5.5V provides margin above 5V for rail-to-rail measurements of signals from legacy systems.
The wide external supply voltage, while maintaining a stable low core voltage for the silicon can be accomplished by providing built-in Low Dropout Regulators within the device. Moreover having separate internal regulators for digital and analog domains ensures that analog performance is not compromised due to noise from the digital power rails. Figure 2 shows the system level connections and internal regulators that accommodates a wide supply voltage range.
Independent power supply for I/O banks
To allow interfacing to other devices in the system that might have different system voltages, an Psoc needs to have separate I/O power rails that can be independently set to any voltage within a wide voltage range. An Psoc that has 4 I/O banks, with each I/O bank able to be driven with any voltage from 1.8V to 5V, provides seamless interfacing to other devices on the PCB
Flexible power modes
While there continues to be a myth that programmable systems are power hungry, well thought-out programmable Psocs can have world class power numbers that match stand-alone MCUs. Keeping the end customer’s application in mind, the power modes that are desirable
In Alternate Active mode, a selected fewer number of peripherals are active. This provides a reduced power active mode that can be entered from the regular Active mode. Upon exit from this mode, the system returns to regular Active mode. An example use case for this is a situation where an embedded system with a display continues to operate while the display alone is turned off. When the display needs to be turned off, the system will enter Alternate Active, where the peripherals needed for the display are turned off.
Sleep is a commonly used mode in battery powered embedded systems. This is an extremely low power mode, where all peripherals are in low power state, while a real-time clock can be maintained. This mode is also used for systems that need to be duty cycled between active and sleep constantly. An example use case is a temperature sensor that needs to update itsreading every minute. The system wakes up every minute, takes the reading and goes back to sleep. This results in reduced average power.
Hibernate is the lowest power consumption mode of the device while memory contents and configuration can still be maintained. The ability to wake-up from an I/O source provides the ability for the user or another device in the system to wake the device up. Hibernate mode can also be used to eliminate a power switch in a handheld device (since the device can wakeup on any button press).
Conclusion
A programmable Psoc offers high levels of integration and at the same time provides the user the ability to build their own custom peripherals using a highly configurable and programmable system. Carefully designed programmable Psocs can offer world-class power management features that not only meet MCU power numbers but also offer a configurable power management system that can also deliver precise analog performance.
To know more about Embedded Systems visit www.cypress.com
About the Author
Palani Subbiah
